1. Field of the Invention
The present invention relates to a circuit device having a self-testing function, and a testing method thereof. Particularly, it relates to a circuit device and a testing method thereof by which a plurality of circuits to be tested contained in the device can be tested for a short period of time.
2. Description of the Prior Art
In a semiconductor integrated circuit such as a digital signal processor for receiving and processing an externally applied digital signal, it is necessary to verify operation thereof. Tests for such verification are usually conducted at the time of debugging before manufacturing of semiconductor integrated circuits or at the time of verification of performance before shipment. In such a test in general, a circuit to be tested is operated after predetermined data has been inputted thereto and it is determined based on data outputted therefrom whether the circuit is normally operated or not.
FIG. 1 is a block diagram showing an example of connection in a conventional semiconductor integrated circuit including two circuits to be tested. This semiconductor integrated circuit 8 includes as the two circuits to be tested a first circuit 2 and a second circuit 5. A test is performed by using three scanning registers in the integrated circuit 8, i.e., a first scanning register 1, a second scanning register 4 and a third scanning register 6.
Referring to FIG. 1, a serial input terminal 83 of the integrated circuit 8 is connected to a serial input terminal 13 of the first scanning register 1. On the other hand, parallel input terminals 81 of the integrated circuit 8 are connected to parallel input terminals 1 of the first scanning register 1. Parallel output terminal 12 of the first scanning register 1 are connected to parallel input terminals 21 of the first circuit 2 to be tested. Parallel output terminals 22 of the first circuit 2 to be tested are connected to parallel input terminals 41 of the second scanning register 4. A serial output terminal 14 of the first scanning register 1 is connected to a serial input terminal 43 of the second scanning register 4. Parallel output terminals 42 of the second scanning register 4 are connected to parallel input terminals 51 of the second circuit 5 to be tested. parallel output terminals 52 of the second circuit 5 to be tested are connected to parallel input terminals 61 of the third scanning register 6. A serial output terminal 44 of the second scanning register 4 is connected to a serial input terminal 63 of the third scanning register 6. Parallel output terminals 62 of the third scanning register 6 are connected to parallel output terminals 82 of the integrated circuit 8. A serial output terminal 64 of the third scanning register 6 is connected to a serial output terminal 84 of the integrated circuit 8.
A selection signal generator 9 generates a selection signal Sc for selecting a mode of the scanning registers and supplies it to the first, second and third scanning registers 1, 4 and 6, respectively. A clock generator 7 generates a clock signal .phi. for synchronously operating all of the first, second and third scanning registers 1, 4 and 6 and the first and second circuits 2 and 5 to be tested. The clock signal .phi. is supplied to each of those circuits.
FIG. 2 is a block diagram showing a scanning register (the first scanning register 1 as an example) used for testing of the integrated circuit of FIG. 1.
Referring to FIG. 2, the scanning register 1 comprises registers SL1 to SLn each including a selector 15 and a master-slave latch 16 connected to the corresponding parallel input terminal 11 and the corresponding parallel output terminal 12, respectively. The selector 15 of the register SL1 has two inputs i1 and i2, the one input i1 being connected to the serial input terminal 13 of the scanning register 1 and the other input i2 being connected to the corresponding one of the parallel input terminals 11 of the scanning register 1. The selection signal Sc is supplied to the selector 15. The master-slave latch 16 of the register SL1 has an input connected to an output of the selector 15 and an output connected to the corresponding one of the parallel output terminals 12 of the scanning register 1. The clock signal .phi. is supplied to the master-slave latch 16. The output of the register SL1 is connected to one of the inputs of the selector 15 of the register SL2. Thus, the registers SL2 to SLn are connected in the same manner as described above, except that the output of the last register SLn is connected to the serial output terminal 14 of the scanning register 1.
Now, operation of the scanning register 1 is described. The scanning register 1 operates in a parallel mode (also called an operation mode) or a serial mode (also called a shift mode) in response to the selection signal Sc. Each master-slave latch 16 receives data from the corresponding selector 15 in response to the clock signal .phi. of high level and stores the data in response to the clock signal .phi. of low level.
First, in the parallel mode, each selector 15 selectively receives data supplied to the corresponding input i2 in response to the selection signal Sc of low level instructing the parallel mode and outputs the data to the master-slave latch 16. The master-slave latch 16 latches the data outputted from the selector 15 and outputs the latched data through one of the parallel output terminals 12. Thus, in this case, the registers SL1 to SLn constitute parallel registers operating in response to the clock signal .phi..
On the other hand, in the serial mode, the selector 14 of the register SL1 selectively receives data supplied to the input i1 in response to the selection signal Sc of high level instructing the serial mode and outputs the data to the master-slave latch 16. The respective registers SL2 to SLn receive outputs of the master-slave latches connected at the respective preceding stages by the functioning of the respective selectors. Accordingly, in this case, the registers SL1 to SLn constitute shift registers having n master-slave latches connected serially and operating in response to the clock signal .phi..
FIG. 3 is a block diagram showing an example of a circuit to be tested (the first circuit 2 of FIG. 1).
Referring to FIG. 3, the circuit 2 to be tested comprise an adder 23, a register 24 and a limiter 25 which are connected serially between the parallel input terminals 21 and the parallel output terminals 22.
In operation, data is inputted to the adder 23 through the parallel input terminals 21 in response to the clock signal .phi.. The data obtained through addition is supplied to the register 24 in response to the clock signal .phi. and then limiting processing is applied to the data in the limiter 25. Thus, the circuit to be tested processes the input data and outputs the data in a period of two cycles of the clock signal .phi..
Description is now made of testing operation of the integrated circuit i of FIG. 1 where the scanning registers and the circuits to be tested are connected as described above.
Referring again to FIG. 1, first, the selection signal generator 9 generates a selection signal Sc of low level. All the scanning registers 1, 4 and 6 operate in the serial mode in response to the selection signal Sc. Predetermined test pattern data D1 for testing is supplied to the serial input terminal 83 of the integrated circuit 8. The first scanning register 1 stores the pattern data D1 through its serial input terminal 13 in response to the clock signal .phi.. Then, a selection signal Sc of high level is outputted from the generator 9 and all the scanning registers 1, 4 and 6 operate in the parallel mode. The first scanning register 1 outputs the test pattern data converted to parallel data from the parallel output terminals 12 in response to the clock signal .phi.. The first circuit 2 to be tested performs predetermined operation upon receipt of the parallel test pattern data through the parallel input terminals 21 and outputs the processed data in parallel from the parallel outputs terminals 22. The second scanning register 4 receives the processed data through the parallel input terminals 41 and then the generator 9 outputs a selection signal Sc of low level. The second scanning register 4 converts the processed data to serial data in response to the signal Sc and outputs the serial data from the serial output terminal 44. The third scanning register 6 receives the processed serial data through the serial input terminal 63 and outputs the data from the serial output terminal 64. The data is outputted from the serial output terminal 84 of the integrated circuit 8. The predetermined test pattern data D1 supplied to the serial input terminal 83 and the processed data outputted from the serial output terminal 84 are analyzed, so that it can be verified whether the first circuit 2 to be tested operates normally or not.
After the normal operation of the first circuit 2 has been verified, operation of the second circuit 5 is verified in the same manner. More specifically, predetermined test pattern data D2 supplied through the serial input terminal 83 is supplied to the second scanning register 4 through the first scanning register 1. The second scanning register 4 converts the data D2 to parallel data and then supplies it to the second circuit 5 to be tested. The parallel data processed by the second circuit 5 is supplied to the scanning register 6, where it is converted to serial data. The serial data thus converted and the predetermined test pattern data D2 are analyzed.
FIG. 4 is a flow chart for explaining operation procedures in the integrated circuit of FIG. 1. This flow chart represents operation steps of the integrated shown in FIG. 1 for verifying operations of the first circuit 2 and the second circuit 5 to be tested as described above. In the following, it is assumed that an operation delay time in the first circuit 2 to be tested corresponds to three clocks and that in the second circuit 5 to be tested corresponds to four clocks. In addition, it is assumed that all the scanning registers 1, 4 and 6 have 8-bit input/output terminals. The delay time in each operation step is indicated in the figure on the right side thereof by the count number of clock signals .phi..
Referring to FIG. 4, first in the step 201, all the scanning registers 1, 4 and 6 are set to the serial mode. (In other words, the selection signal generator 9 of FIG. 1 outputs the selection signal Sc of low level.) Then, in the step 202, the test pattern data D1 for the first circuit 2 to be tested is inputted serially to the first scanning register 1. The period of this procedure corresponds to eight clocks. In the step 203, the scanning registers 1, 4 and 6 are set to the parallel mode. (In other words, the selection signal Sc of high level is outputted.) In the step 204, the first circuit 2 to be tested is operated. This procedure takes three clocks. In the step 205, the scanning registers 1, 4 and 6 are set to the serial mode. (The selection signal Sc of low level is outputted.) In the step 206, the data processed by the first circuit 2 to be tested is outputted serially from the output terminal 84 through the second and third scanning registers 4 and 6. This procedure takes 15 clocks. The data from the output terminal 84 and the test pattern data D1 supplied to the input terminal 83 are analyzed, whereby operation of the first circuit 2 is verified.
Then, in the step 207, the test pattern data D2 for the second circuit to be tested is inputted serially to the second scanning register 4 through the first scanning register 1. This step takes 16 clocks. In the step 208, the scanning registers 1, 4 and 6 are set to the parallel mode. (The selection signal Sc of high level is outputted.) In the step 209, the second circuit 5 to be tested is operated. This procedure corresponds to four clocks. In the step 210, the scanning registers 1, 4 and 6 are set to the serial mode. (The selection signal Sc of low level is outputted.) In the step 211, the data processed by the second circuit 5 to be tested is outputted to the output terminal 84 through the third scanning register 6. This takes seven clocks. The data from the output terminal 84 and the test pattern data D2 supplied to the input terminal 83 are analyzed, so that operation of the second circuit 5 is verified.
As described above, in the prior art, if two or more circuits to be tested exist in an integrated circuit, verification of operation is effected individually for each circuit to be tested, i.e., for each of the first and second circuits 2 and 5 to be tested. In the above described conventional example, a period corresponding to 53 clocks in total is required for verification of the operations of the two circuits 2 and 5 to be tested. If a large number of circuits to be tested are included in the integrated circuit, a period required for verification of operation is increased in proportion to the number of circuits to be tested.
An example of the prior art of particular interest to the present invention is shown "LSI/VSLI TESTABILITY DESIGN" (pp. 102-109) by Frank F. Tusi published by McGraw-Hill, Inc. in 1987. This document indicates, concerning the Scan-Path (including Scan-In and Scan-Out), procedures in which a predetermined pattern is set in an internal register of a system and then the content of the register is read out to an external portion through testing of the system.
Another example of the prior art of particular interest is found in "INTRODUCTION TO VLSI SYSTEMS" by Carver Mead et al. published by Addison-Wesley Publishing Company, Inc. in 1980. In pages 75 and 76 of this document, transfer of data between two registers through a pipe line is described in which different data sets are processed simultaneously in the system since the registers and combinational logic circuits are connected alternately. In addition, in pages 66 and 67 of this document, fundamental operation of shift registers is described.